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Solid States Devices => solid state devices => Topic started by: ayeaye on September 29, 2015, 03:26:51 AM
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Below is the circuit symbol of a mosfet (an n-channel mosfet). The two input capacitances of the mosfet can be seen on that symbol, as circled there. The gate-source capacitance is greater of these.
Mosfet can leak at two times. When switching on, then the input capacitances are charged, when the mosfet still has a high resistance. This period is very short though, as mosfet switches on fast, and its resistance when it is switched on, is extremely small, so there is no considerable leakage then.
The second time is when the mosfet is switching off. Then its input capacitances discharge, but this doesn't happen instantly, so some current goes to the circuit. For the circuit the input capacitances are connected in series. The input capacitance of a mosfet is quite great, may be some 500pF.
I wrote it for not to avoid mosfets to be used in the overunity experiments. Their switching is very fast, and they are the most widely used transistors. When the output power gain of the circuit is more than the energy necessary for charging the mosfet's input capacitance once in a switching cycle, then i think that it's quite certain that there is an overunity. The same as bipolar transistors, they leak, but this leakage has to be considered in the circuits and calculations.
Saying that, it looks like, when looking at the simulation diagrams, that mosfet also has some 42 k ohms resistance, between the gate and the drain. So maybe that should be also considered. And it also looks like that it doesn't leak when switched off, at all. Or maybe it only leaks because of that resistance.
I hope that what i wrote here would be useful for someone for some purpose. Sorry if not.
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Ok, i now simulated it with ngspice (gEDA), to find out, the first figure below is the simulated test circuit. The third figure below shows the currents in the simulated circuit, blue is the current in the circuit, and red is the gate circuit. When talking about currents here hereafter, it is about positive currents, which is considered to be conventional. The direction of the currents on that diagram is what is considered positive, for the gate current, the current towards the gate, and for the current in the circuit, the current which is considered positive for the mosfet, that is current towards its source. The 600 units on that diagram is 600 uA. The second figure below is the equivalent circuit of the mosfet.
Look at the currents diagram. The current direction in the circuit is always opposite to the change of the gate current. And the shapes of the signal are rounded and delayed. This can only be inductance, nothing else. And look at the mosfet's equivalent circuit, there is an inductance Ls before the source.
So it now seems to be clear how the leaking happens. What is important for leaking is only the gate-source capacitance Cgs, and the inductance before the source Ls. Notice that in the circuit, Cgs is not connected directly to the ground, but there is Ls between it and the ground. This causes the leakage exactly as it happens, and i will explain how.
In the test circuit, when Cgs charges, there is an increase of current towards the ground. This increase of current current induces current in Ls in the opposite direction, away from the ground, and this current goes to the circuit. That current on the currents diagram has exactly that direction.
When Cgs discharges, there is an increase of current away from the ground. This increase of current current induces current in Ls in the opposite direction, towards the ground. That current on the currents diagram has exactly that direction.
So by that, mosfet leaks because of Cgs and Ls, and not considerably in any other way. The capacitance Cgs can be calculated from the data in the mosfet's datasheet. The inductance of Ls can be calculated based on the test results. It also should appear in the mosfet's spice model. And based on Cgs and Ls it can be calculated how much the mosfet leaks in any particular circuit.
So TinselKoala, you were wrong wrong wrong. Mosfet doesn't leak because its internal capacitances, but because of its internal capacitances *and* its internal inductance. The mosfet's leakage is mostly said to be because of its internal capacitances, and this causes a huge confusion and makes completely impossible to understand what happens in some circuits. Because leakage due to capacitance and leakage due to capacitance and inductance are completely different, they behave in completely different ways. And the direction of some currents is the direct opposite.
Hope that this could help anyone. Sorry if not.
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No, I am not "wrong wrong wrong". Your simulations actually show that I am "right right right".
But whatever. You can continue to fool yourself all you like, I'm tired of playing this silly game.
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I was not serious but, i think anyone who has to do with electronics knows, that circuits that contain only capacitors, and circuits that contain both capacitors and coils, behave very differently.
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Here's your proof. I've taken an unused IRF624A mosfet (grabbed at random from my New Parts Stock Tin) and connected the FG's Red output lead to the Gate of the mosfet, and connected the CH1 Scope Probe to the Source of the mosfet. Nothing is connected to the Drain and there are no other components used. The FG's Black output lead and the Scope Probe Ground leads are clipped together. The FG is set to produce a positive (DC) pulse train of about 2V peak. CH1 is the signal at the Source pin of the mosfet and CH2 is the signal coming from the FG, directly connected to the scope via a BNC patch cable (no probe). Note that the CH1 signal is _AC_ and is _in phase_ with the raw FG output. This indicates that the mosfet is acting like a capacitor, passing the signal from the FG on the Gate, through to the Source.
Certainly, the inductances of the mosfet and its connecting leads must be taken into consideration in any _true_ simulation of the mosfet's behaviour, but the leakage I have always been talking about is the Cgs leakage from Gate to Source due to the capacitances of the mosfet.
So, what.
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Yes, as you see on the currents diagram, the opposite current caused by the inductance is much less than the charging and discharging current of Cgs. Also, the inductance doesn't work very well when it doesn't have a closed circuit with a low resistance, and your circuit through drain-source has an almost infinite resistance. So your test mostly shows passing voltage through the capacitance.
Yet, in your channel one, do you notice that the upper edges of the pulses go slightly down, and the lower edges after pulses slightly rise? This is likely the effect of the inductance, because inductance works against the change of voltage, it tries to bring it down after it rises, and to bring it up, after it falls.
If you are interested, below is the diagram from the same simulation i did before, of the voltages at the output of the pulse voltage source (blue) and at the gate (red), between them is a 10k resistor. The voltage at the gate mostly shows the charging and discharging of Cgs with exponential curves. Yet, we see the inductance at the end of the discharge, where the voltage very slightly rises. We should also see it at the end of the charge, but this weird horizontal line makes it impossible to see. I don't know what it is. Because of inductance there should be a decrease of the rise of the voltage slightly more than by the exponential curve.
But, about the mosfet leaking, the mosfet did not anyhow considerably leak without the inductance, this seems to be the point.
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When you say "weird horizontal line" are you referring to the Miller plateau?
Maybe this Vishay application note will help.
http://www.vishay.com/docs/73217/73217.pdf
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Yet, in your channel one, do you notice that the upper edges of the pulses go slightly down, and the lower edges after pulses slightly rise? This is likely the effect of the inductance, because inductance works against the change of voltage, it tries to bring it down after it rises, and to bring it up, after it falls.
There is substantially more inductance in the probe connections, particularly the Ground clip wire, than there is in the mosfet itself.
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Here's another example from real life. You can clearly see the Miller plateaus, as well as the inductive switching transient ringing at the end of the pulse.
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Thanks for your info about the Miller plateau. As much as i understand, this has to do with the increase of capacitance during the channel formation. As i understand, the capacitance is not only between the electrodes, but also the n regions or something, so when they grow, the capacitance grows.
Well, my primitive understanding of the mosfet, n-mosfet, it consists of a p semiconductor, or as i prefer to say, p-conductor, which though is only slightly p, or something, so it almost doesn't conduct. Then, the positive charge at the gate attracts electrons into it, making it an n-conductor, which forms a conducting channel between the source and the drain.
I prefer to say n-conductor, because the prefix "semi" is very misleading in the word semiconductor. They are conductors, but different from metals where electrons form an electron gas, the electrons there are tied to atoms, and hop from one atom to the other, something. Now this can happen when there is either excess of elecrons, or lack of electrons. In the latter case an electron jumps to the next atom to fill the lack of electrons there, called a hole, and leaves a hole behind in the atom where it jumped from, this is a p-conductor.
The inductances in the mosfets have to do with connecting the electrodes to the pins, something. By the irf530n datasheet http://www.irf.com/product-info/datasheets/data/irf530n.pdf (http://www.irf.com/product-info/datasheets/data/irf530n.pdf) the source inductance Ls in that mosfet is 7.5 nH. A very low inductance, i wonder that it causes so considerable effect. The drain inductance Ld is 4.5 nH.
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That's right, very low. Most of the inductive effects associated with mosfets come from the circuit they are connected to, like the lead wires and circuit board traces, or in the case of scoping, from the probe's ground clip wire. A few inches of wire, or improperly routed PCB traces, will have more inductance than is found in the mosfet itself. However, the Gate-Source capacitance is significant.
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Ok, i guess you are right, the inductances in the mosfet are too small to cause any considerable effect.
Then i think the only thing that can cause the mosfet leaking, is the gate-drain capacitance, Cgd. Cgd is the same as Crss in the datasheet http://www.irf.com/product-info/datasheets/data/irf530n.pdf (http://www.irf.com/product-info/datasheets/data/irf530n.pdf), which means that with the gate-source voltage Vds 25V, it is 19pF. But by the figure 5 there, when Vds is 0, this capacitance is 400pF.
Consider a negative current, that is movement of negative particles. And consider that positive direction of the current in the circuit is positive direction for the mosfet, that is drain to source. It is not because the current necessarily goes through the mosfet at all, it is just about direction, to determine the direction. The diagram below shows the current at the gate (red) and the current in the circuit (blue), the 600 units there is 600 mA.
Now what i think happens. When Cgd charges after the start of the pulse, there is current in the negative direction. When Cgd discharges after the end of the pulse, there is current in the positive direction. The directions are such because when the mosfet has a high resistance, one may think that the current only goes from the ground to Cgd through the circuit, or from Cgd to the ground through the circuit.
But why the curves of charging and discharging in the circuit (blue) are not typical exponential. There are two things that happen. First the resistance of the mosfet changes, the lesser it is, the less is resistance between Gds and the ground, and less current goes through the circuit. Second, the capacitance of Gds changes.
What concerns the current curves, the current rises when the pulse starts and there is voltage on the gate. This does not yet open the mosfet though, mosfet opens when the input capacitances are charged so that the voltage on them rises above a certain level. When that happens, the Miller plateau starts. At the end of the Miller plateau, the mosfet is fully open. One can see on the currents diagram, that the current in the circuit goes to zero at that point, because the resistance of the mosfet is close to zero then, and Gds can by all practical means then be considred to be connected to the ground.
I also tried to illustrate it for you on the first figure below to show how the mosfet leaks, hope that helps.
Does that make sense?
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Ok, no one said that it doesn't make sense.
Now see this.
I did the simulation as before with ngspice, except the circuit was that in the diagram below. I did transient analysis tran 0.1ns 150us and then plotted two different parts of the switching cycle, at the beginning of the pulse in the second figure below, and after the end of the pulse in the third figure below. The diagrams are as before, red is the current at the gate, blue is the current in the circuit, and units are amperes.
As you see, the current in the circuit goes at the beginning of the pulse to 30 mA, but this lasts only 45ns. As you see, at 25ns the mosfet opens, and the Miller plateau starts. The current in the circuit goes to zero at the end of the Miller plateau, when the resistance of the mosfet is almost zero, and Cgd is almost connected to the ground.
The current has almost a triangle shape. So we can calculate root mean square for the triangular wave, a / sqrt(3), the current by that is 17.32mA. The energy leaked into the circuit is I * I * R * t, and this is 1.3nJ.
As you see, at the end of the pulse the current in the circuit goes to 0.5mA, and stays there for 1us. We can consider that the current is almost constant during that time. The energy is I * I * R * t, and this is 2.5nJ.
So the total leaked energy was 3.8nJ. This is the energy necessary for charging a capacitance 0.3pF to 5V. In spite that Cgd, even when the mosfet is fully open, is 19pF, because the time of the mosfet's opening is very short, much less energy can go to that capacitance while the mosfet is still partly closed.
As you see, the energy leaking from the mosfet is very small, so small that sometimes it may even be completey dismissed when calculating a power gain. Power gain inside the circuit that is, not considering the power necessary for switching the mosfet, calculating this in-circuit power gain is important for theoretical reasons.
The leaked energy depends on the impedance of the circuit though, as with a lower impedance the current is higher, and thus more energy can go to Cgd during the time when mosfet is still open. But the resistance of the tested circuit was quite low, only 100 ohms. So if you add a 100 ohms resistor to your circuit, then likely no more energy can leak to the circuit.
The netlist was as follows.
* Spice netlister for gnetlist
.SUBCKT irf530n 1 2 3
**************************************
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
**************************************
* Model generated on Sep 21, 01
* MODEL FORMAT: SPICE3
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=3.79209 LAMBDA=3.64034 KP=81.097
+CGSO=8.9e-06 CGDO=1e-11
RS 8 3 0.056205
D1 3 1 MD
.MODEL MD D IS=9.06112e-12 RS=0.00982324 N=1.13042 BV=100
+IBV=0.00025 EG=1.2 XTI=3.54513 TT=0.0001
+CJO=7.4e-10 VJ=1.52632 M=0.693198 FC=0.5
RDS 3 1 1e+06
RD 9 1 0.0219755
RG 2 7 4.4648
D2 4 5 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=9.44672e-10 VJ=0.5 M=0.9 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.400249 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 1.29816e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.400249
.ENDS irf530n
V1 n0 0 dc 0 pulse 0 5 0 25n 25n 100u 1m
X1 n2 n1 0 irf530n
R2 0 n2 100
R1 n0 n1 1
.END
So i think the myth of the great mosfet leaking is now destroyed.
Thank you for your attention, or maybe interest, hope it was useful for someone for some purpose. Sorry if not. Have a good time, and do experiments.
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In the previous post, the leaking energy after the pulse should have been 25pJ. So the total leaked energy during one switching cycle with the circuit resistance 100 ohms, was 1.3nJ.
I also did the same simulation to find out the leaking energy with the circuit resistance 55k. Then the leaked energy at the beginning of the pulse was 2pJ, and the leaked energy after the end of the pulse was 700pJ. So the total leaked energy during one switching cycle with the circuit resistance 55k, was 0.7nJ.
When there are capacitors and coils in the circuit, then what likely matters is the impedance of the circuit. For calculating the impedance, first find the longest curve in the current diagram, like the longest curve above zero, and find its length in time t. Then the minimum frequency should be f = 1 / (2 * t) . With higher frequency, the impedance of capacitors is very small. For coils, the impedance of a coil in ohms is 2 * pi * f * L , where L is the inductance of the coil in henries. Mosfet leakage with that impedance should be the same as with a resistor with the same resistance, by the resistance equivalence. Maybe some don't agree, but should be so by logic.
So i hope that now by knowing that, many avoid the pain that i had due to the mosfet leaking, all like hanged in the air, there was no way to find the real mosfet leaking to the circuit. No more so for these who do experiments now i think, and they can use mosfets because of their very fast switching, at least for initial evaluation.
The energy necessary for switching the mosfet is by that written above much greater than the leaking energy, but most of that is just wasted and goes to the ground at the end of the pulse. Like for the mosfet irf530n, the input capacitance is 900pF, and thus the switching energy in every switching cycle should be 11uJ, which is a lot. But for a theoretical research, only the energy in the circuit matters, and thus only the leaking energy can be considered, which by that above is much less. Yet even 0.7nJ in every switching cycle may cause some remarkable effects, so always find the mosfet's leaking energy before doing the experiments.
Hope it was useful for some.
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Helpful would be the proven circuit to switch mosfet at nanoseconds time (below 100ns) :P
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Helpful would be the proven circuit to switch mosfet at nanoseconds time (below 100ns) :P
Ok, simulated with 100 ohms circuit resistance, the pulse voltage source was
dc 0 pulse 0 5 0 5n 5n 10n 700n
Which means 5V positive pulses, with the initial delay 0, rise time 5ns, fall time 5ns, and length 10ns. Which means that the total length of the pulse was 20ns. The cycle length was 700ns. The transient analysis was done with
tran 1ns 700ns
Which means transient analysis during 700ns with 1ns steps. The current in the circuit in the ngspice diagram below, is clockwise. But calculate yourself please.
For these who have not used ngspice before, helpful may also be the thread that i created about ngspice here http://overunity.com/16064/ngspice-and-geda-circuit-simulation/#.VhFThW943iY (http://overunity.com/16064/ngspice-and-geda-circuit-simulation/#.VhFThW943iY) .
PS Why the capacitance Cgd decreases when the mosfet opens, i think i didn't describe it well before. The n channel mosfet consists of a slightly p semiconductor, but at the source and gate electrodes, there are n areas. This n area conducts, and thus it is like an extension to the capacitance's plate. When the mosfet opens and a current starts to go through it, more electrons come and these n areas widen, and thus the gate side plate of the capacitance decreases. This is also what should cause the Miller plateau. It's just as i see it by now.
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I think i didn't say it quite right again. It looks like when the mosfet opens and current starts to go through it, then the n areas decrease. The decreasing of the n areas also causes the decrease of the input capacitances, and the Miller plateau. The n areas conduct, remember. And the p area is only slightly p, so it doesn't conduct. Why, because the electrons that come to the p area and make it conductive, come from the n areas. At least this is how i understand it by now.
I had to explain it, because i think one should know what happens there. This is not anything high level. It's just mechanical. Like understanding how a coffee machine works. It's only necessary to know what exactly happens.
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I don't understand it all ;-) but I feel that keeping mosfet right around the Miller plateau would allo very fast opening/closing. Am I right ? I know there are scientific papers about circuits switching ordinary mosfets (with trr time in the 2us range) in 5ns
We should concentrate on this, at least i would if I had a team working on solutions :-)
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I feel that keeping mosfet right around the Miller plateau would allo very fast opening/closing.
Yes i guess. And should decrease the input energy too, as all the charge in Cgs gets wasted when the input goes to zero, and it will be completely discharged to ground. And should also decrease the leaking to the circuit after the pulse, because Cgd will also not be fully discharged.
If you don't understand the leaking, then think about it like this. When the (n-) mosfet is closed, then all the circuit is really connected from the ground to the drain. When we charge Cgd, then the current goes from the ground to drain. And when we discharge Cgd, then the current goes from the drain to ground. This evidently is all the leaking to the circuit there.
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My hand drawing was a kind of bad, so i added below a drawing made with gschem, which explains mosfet leaking. I hope that all understand it now.
On that drawing, Cgd is not a capacitor, but the (n) mosfet's gate to drain capacitance. Mosfet is not drawn, because on both diagrams above and below, it is closed, that is, it is the same as not connected. The gate to drain capacitance is in both cases connected to the ground, so the leaking to the circuit does not depend on it anyhow.
The arrow shows on both diagrams the direction of the negative current, that is current which is considered to be a movement of negative particles.
Hope it was useful for someone for some purpose.