I had an idea come to mind the other day, I'm sure I'm missing something or it's been thought of already; but who knows. I figured I'd post to see if it may work or help someone's design. I'm a bit crusty on EE and am not overly accomplished in circuits. The most advanced circuit with some help was a adjustable frequency / voltage flyback driver, but that was a while ago; TC's also, but not SS.

At any rate I've gone over somethings and done a few numbers and I believe this may work. I've drawn a block circuit to help represent the thought here, also a hand drawing of the frequencies relative to time.

The first and most important thing. I show SSSG or SISG's in the diagram, though there is probably a device more suited for low power. However it could be possible to only work on HV if there is not such a device. Essentially though, when these devices are off (open) they need to be totally disconnected from the circuit; with the exception of an obvious junction capacitance. What I mean here is, there cannot be a reverse leakage current as you would see from a diode or some transistors. The coil then is, and must be, able to freely resonate.

To start then from the right side of the diagram (all SISG open); we have a sine wave input of your chosen frequency. This should be a fractional odd multiple of the Coils' (L1) self resonant frequency (F2). With the Right 2 SISG's closed you have a series LCR with L1 and C1; which creates this fractional multiple F1. Power is applied for 1/4 cycle, or to full (first half wave) voltage. At that point the 2 SISG's on the right open and allow the coil to collapse the field at its' self resonant frequency F2 (flyback). The frequency of this collapse is higher, since you'd only have the junction capacitance from the SISG's and the L1 capacitance. Again, this should be the first chosen, dominate frequency. Once enough time has passed for this coil to "swing" to its' full voltage (1/4 wave); the 4 SISG's on the left connect to the coil in split segments. These segments should be an odd multiple of the coils turns or length. Once these SISG's on the left are connected, we have a Parallel LCR with L1 (sections) and C2's of a third frequency F3; again this too should be an odd multiple of the F2. This frequency, though being odd, is still a larger fraction as compared to the charging side F1. As with all other stages, these circuits are connected for 1/4 wave to reach full voltage. After all of this, the input frequency should be ready for its' second half cycle and the process would repeat with opposite electrical flow through L1. Finally, the SISG's on the far left, leading to the rectifiers; can be connected to C2 until voltage reaches 0, or when C2 needs to be connected to the coil. Basically they can be connected for a longer time and only must be open when the SISG's connect to the coil with C2.

Since induced voltages in coils is based on the rate of change per unit time and a disconnection of the circuit allows for an increase in the rate of change; it also creates then a voltage increase. I know everyone is aware of this. For simplicity sake with an example; lets assume all sine waves and also to the increase in voltage simply to, the change in frequency from the charge side(F1). Obviously you will have resistive losses in the coil and core along with parasitic losses to the SISG's, though they should be small at lower frequencies and also would be beneficial to use low loss cores.

I kinda rattled this around in my head for a while and haven't found where it won't work. I suppose the SISG would be the most important; though you could use a rotary gap (lol) to accomplish the same purpose (commutator). Again, I'm sure there's a device suited for this but I don't know what's best. If not, then you would have to run this on HV and use real SSSG's, or SISG's.

L2 is just shown as an example to use feedback to drive your timers. This should NOT be attached to the coil and would probably need both an amp and a 180 degree inversion for operation. It may help with design, I'm not sure.

At any rate to give an example here using calculators online and with the pictures shown;

Input F1 = 100hz @ 10v. L1= 1H, C1= 7uF / Z= 376.99 - 26.5ma (1/9th)

Self Resonant F2 = 900hz @ 90v. L1= 1H, Self capacitance total max 31nF / Z= 5654.87 (dominate)

Output F3 = 150hz @ 30v ea. L1 = .333H ea, C2 = 3.377uF ea / Z= 314.16 - 95.5ma (1/6th)

If you can create this circuit then, the number show. 10v @ 26.5ma input .26w and the output would be 30v @ 95.5ma or 2.86w times 3. This means an increase of 11 times per C2 in this set!? Seems like enough of an increase to overcome losses though. Assuming of course the SISG switches act as truely open and allow the coil to resonate.

Advantageously, using this shown setup and frequencies; you will most probably setup 3 (tiny) standing waves on the coil which should reinforce things a bit.

The keys of course would be to allow the coil to resonate on open circuits, odd multiples, timing and a low loss core.

Last shown in my crappy pencil drawing, is the three example frequencies and their half wave times and initiation points. The largest is 100hz F1 and has the first dotted line to show "cut point" (e.g. 1/4 wave). The space between the first two dotted lines is the time for self resonating and shows the 900hz smallest hump. At the point in time of the second dotted line is when you connect to C2's and have the 150hz begin its' quarter wave. You can see on the far right there is exactly one half wave of the dominate F2 frequency after the C2 connection is cut. These of course would represent when the SISG's open and close, and for how long.

So ya, has this been tried; or does anyone have thoughts on this? I'd say this is outta my league for circuit design so I can only provide an idea. But as far as I can see, there's no reason why this cannot work. Hope someone can use it!

thanks

EDIT: I got to thinking I should clarify and add another thing I forgot. Duty cycle. First, though I am using half cycle AC voltages, but also only using those in calculations; so AC would technically be considered 20v, 180v and 60v P-P respectively.

Also, duty cycle helps to make a better calculation for power rather than apparent from above.

F1 Duty cycle 25%

F2 Duty cycle 2.7%

F3 Duty cycle 17%

Using 100% duty cycle for input we still have .26w and apparent power from above times duty would give an rms of .487w appx. PER C2. That's the last thing I can think of to ruin this being possible but still works even with 100% duty input; even though it's only 25%.

Also, 4 of these circuits could fully use the input frequency and all its cycles. E.g. at each quarter wave, you'd connect the F1 drive to another circuit; then you could get 100% duty out of the input.

EDIT 2: I guess if you also used the second half of the cycle your duties would be higher. Double in fact (34% for F3) and would give then an rms of .974w per C2. So it's advantageous to use both half cycles. That means a continual output of close to 1 watt PER each C2 capacitor. So 3w rms out from a .13w rms input.