Author Topic: Testing the TK Tar Baby (Read 2008558 times)

TinselKoala · « **Reply #420 on:** April 19, 2012, 08:34:25 PM »

Quote from: picowatt on April 19, 2012, 08:22:35 PM

.99,

I have suggested a few times that a 50R be placed in the source leg of Q2 and that the gate be biased at a positive voltage to keep Q2 operating (similar to your circuit). A 1meg pot across the first Batt+ with the wiper tied to the gate circuit (AC decoupled) would allow the operating bias of Q2 to be set/varied. This would only draw 12-14ua. from the first battery (depending on its voltage). Alternately, the gate coud be tied to the first Batt+ directly through a series resistor/cap to ground (for decoupling) and only the decoupling cap and gate leakage current would be drawn from the first battery. The value of the 50R at the source could be modified to set the Q2 operating (bias) current.

PW

I agree, this would be a good way to make stable and adjustable oscillations, better than the simple battery-pot idea (which does work but is kind of twitchy). But if this is done, obviously the power contribution of the bias source is eliminated. Is it then a NERD circuit any more? This is why I didn't pursue the optocoupler idea earlier. I think now I could get it to work, but again... the isolation defeats the functioning of the NERD circuit.
This is also my objection to MH's LEDs of Doom. The LED is a diode after all, rectifying what it sees ... and inserting it into the circuit, even bidirectionally, might interfere with the "normal" current paths and thus void the warranty.

picowatt · « **Reply #421 on:** April 19, 2012, 09:08:36 PM »

Quote from: TinselKoala on April 19, 2012, 08:27:51 PM

Hmmm... I think I'm understanding this a bit more now.

The negative potential on the Q2 source pins effectively increases the potential difference between the gate and the source, with the gate being more positive... even though it's held at "zero" volts by the gate drive pulsation baseline. When the negative potential on Q2 source becomes great enough-- 4 or so volts negative wrt the gate at "zero" volts.... the mosfets begin to conduct a little and the oscillations start. Once the oscs start they provide a rising and falling potential difference between the Q2 gates and sources.... in other words, feedback oscillations.

In other words, PW and .99 seem to be describing the same thing, from different sides of the coin, if I am understanding correctly.

Is the power from the negative bias source being mixed in with the main battery power being partially switched by the mosfets during the oscillations? How does this happen if it does? Is it coupled capacitatively through the gate-drain capacitance?

TK,

Hey, I thought you had "real work" to do today!

Your questions are good ones. Regarding the bias source, that is why I asked what your 555 circuit's supply was drawing when it has Q2 oscillating. If your Q2 bias is 150ma. for example, I would think your 555 supply will be showing a total current draw equal to the 150ma bias current plus 555 quiescent current.

For DC, the current path is through whatever is providing the turn on bias supply for Q2. For AC, the path is through both the bias supply and the Ciss of the MOSFETs. When the FG was used, its Rgen=50R was a lesser path for AC than the Ciss of the MOSFETs. With your 555's 10R source, the 10R is probably close to an equal path for AC, as the 10R is close to the Ciss reactance at 1.5MHz.

PW

picowatt · « **Reply #422 on:** April 19, 2012, 09:33:29 PM »

TK,

If you look at the first paper's schematic, it at first appears that the only path for AC at the source of Q2 is through the FG. But, if you draw in the gate to source capacitance, Ciss, you will see that the Ciss is effectively across the FG terminals and therefore allows a portion of the AC current to bypass the FG. The Ciss of a single IRFPG50 is somewhere around 2800pF. Four Q2's in parallel make the total Ciss around 11,200pF, and at 1.5Mhz, this represents a fairly low impedance path around the FG's 50R.

I am still considering how the drain to gate capacitance, Coss, comes into play. Coss will allow an amount of AC to be applied to the CSR, and hence thru the FG and Ciss, effectively be negative feedback. Add some phase shift (inductance) and negative feedback can easily become positive feedback, i.e., an oscillator.

The amount of negative feedback at AC that Coss provides is a bit complicated, as the inductance of the CSR, the DC resistance of the CSR, the reactance of Ciss, the Rgen, and any stray inductance/capacitance would all come into play in dividing the negative FB and setting the Q2 AC gain or alternately, and/or as well, providing the phase shift necessary to cause the oscillation. That is how I see it anyway.

.99 could probably be more quantitative in this regard with his sim probing.

PW

poynt99 · « **Reply #423 on:** April 19, 2012, 09:34:03 PM »

Just to clarify one point;

"bias" means a certain amount of pos. DC V_GS. This can be completely floating wrt the rest of the circuit.

So HOW you provide that bias, makes no difference whatsoever, it can be positive, negative, as long as V_GS is slightly positive, say about 5V.

I have simulated both cases, where the bias is applied to the Source and the Gate. In other words, I have proven what I wrote above.

poynt99 · « **Reply #424 on:** April 19, 2012, 09:54:15 PM »

Quote from: picowatt on April 19, 2012, 09:33:29 PM

.99 could probably be more quantitative in this regard with his sim probing.

PW

If you want to see something specific on any of the circuits, simply ask.

picowatt · « **Reply #425 on:** April 19, 2012, 10:10:15 PM »

Quote from: poynt99 on April 19, 2012, 09:34:03 PM

Just to clarify one point;

"bias" means a certain amount of pos. DC V_GS. This can be completely floating wrt the rest of the circuit.

So HOW you provide that bias, makes no difference whatsoever, it can be positive, negative, as long as V_GS is slightly positive, say about 5V.

I have simulated both cases, where the bias is applied to the Source and the Gate. In other words, I have proven what I wrote above.

.99,

I agree with the comments above, however, the gate is a very high impedance node for DC, while the source is a low impedance node for DC.

In your sim work, if you insert a -12V battery in series with 50R in the Q2 source leg (using the grounded gate configuration and connecting the battery/resistor where the FG is normally connected), wil not the -12V battery have to provide an amount of current equal to whatever DC current is flowing thru Q2?

Personally, I have no problem with the alternate bias method. Tie the gate to the first Batt+ through some decoupling and insert a 50R at the source. I would indeed be impressed if that circuit "ran forever".

PW

poynt99 · « **Reply #426 on:** April 19, 2012, 10:17:18 PM »

Quote from: picowatt on April 19, 2012, 10:10:15 PM

In your sim work, if you insert a -12V battery in series with 50R in the Q2 source leg (using the grounded gate configuration and connecting the battery/resistor where the FG is normally connected), wil not the -12V battery have to provide an amount of current equal to whatever DC current is flowing thru Q2?

Yes, whatever is in the SOURCE will have to pass the Source current. That goes without saying. However, that current has nothing explicitly to do with biasing the MOSFET in a partially ON state. In this instance, the FG (if you will) is providing two functions; V_GS bias, AND AC/DC path to ground.

picowatt · « **Reply #427 on:** April 19, 2012, 10:20:35 PM »

Quote from: poynt99 on April 19, 2012, 09:34:03 PM

Just to clarify one point;

"bias" means a certain amount of pos. DC V_GS. This can be completely floating wrt the rest of the circuit.

So HOW you provide that bias, makes no difference whatsoever, it can be positive, negative, as long as V_GS is slightly positive, say about 5V.

I have simulated both cases, where the bias is applied to the Source and the Gate. In other words, I have proven what I wrote above.

.99,

To further clarify, yes, the bias voltage or Vbias is the voltage applied to the gate relative to the source, i.e., Vgs. But, but the bias current, Ibias, is the quiescent DC operating current that Q2 passes when, in concert with its source resistance and Vds, Vbias is applied.

PW

picowatt · « **Reply #428 on:** April 19, 2012, 10:28:32 PM »

Quote from: poynt99 on April 19, 2012, 10:17:18 PM

Yes, whatever is in the SOURCE will have to pass the Source current. That goes without saying. However, that current has nothing explicitly to do with biasing the MOSFET in a partially ON state. In this instance, the FG (if you will) is providing two functions; V_GS bias, AND AC/DC path to ground.

.99,

I would rather say "two functions; Vgs bias, the only DC path to ground and a partial AC path to ground", the other AC path being Ciss.

Regarding the bias source in the Q2 source leg, if we connect a 15 volt battery in series with 50R between ground (CSR) and the source of Q2 (batt+ at CSR), the measured drop across the 50R will be around 10.5 to 10 volts (the 15volts minus Vgs). That means there is around 200ma flowing as Ibias thru Q2, and as well through the battery. If the battery is a 200ma/Hr battery, does this not mean the battery will last only 1 hour?

PW

(corrected batt- to batt+)

TinselKoala · « **Reply #429 on:** April 19, 2012, 10:39:21 PM »

Quote from: picowatt on April 19, 2012, 09:08:36 PM

TK,

Hey, I thought you had "real work" to do today!

Your questions are good ones. Regarding the bias source, that is why I asked what your 555 circuit's supply was drawing when it has Q2 oscillating. If your Q2 bias is 150ma. for example, I would think your 555 supply will be showing a total current draw equal to the 150ma bias current plus 555 quiescent current.

For DC, the current path is through whatever is providing the turn on bias supply for Q2. For AC, the path is through both the bias supply and the Ciss of the MOSFETs. When the FG was used, its Rgen=50R was a lesser path for AC than the Ciss of the MOSFETs. With your 555's 10R source, the 10R is probably close to an equal path for AC, as the 10R is close to the Ciss reactance at 1.5MHz.

PW

Thanks... I think I get it..... maybe..... So the bias power is "mixed in " with the main power from the batteries and must be dissipated in the load and mosfets (I suspect in the mosfets mostly). Hence the load heating and current viewing resistors are giving an inaccurate picture of the power flows in the circuit.... is that right?
(I know this has been covered before; I just want to hammer it home somehow if it is correct.)

I'm running so late that there's no point in making the drive. So here I am, stuck in Mobile with the Memphis blues again.

Anyway.... I tried the 50r/pot/cap/main battery thing and I can't get it to work. And yes, I've confirmed that the pot is good and is adjusting the voltage properly, tried with three different valued pots.

This _does_ work just fine with the external battery (no decoupling cap), but using the running battery I can't get it to work. External 9v gives beautiful nearly perfect sinusoidal oscillations on the common drain when the 10 k (not 1 meg; I also tried 100 K, no luck) pot is set right, and the "voltage floor" still shows up: the negative voltage on the gate drive signal floors at about 4 volts negative indicated on the scope trace.

I think you really do need to provide a potential that is more negative than the negative battery terminal....

I just made another video... chaotic but the points come through I hope. It's uploading now.

hartiberlin · « **Reply #430 on:** April 19, 2012, 10:39:56 PM »

Is the 200 mA really a DC current ?
What about the AC component flowing while the oscillations are happening ?

If we would use just a 9 Volts battery with a pot and put on the oscillations,
then we would pronbly only have an AC current, right ?
Or will we have an AC current superimposed on a DC 200 mA current ?

Maybe TK can measure this and show it on a new video ?

Many thanks.

Regards, Stefan.

picowatt · « **Reply #431 on:** April 19, 2012, 10:47:48 PM »

Quote from: TinselKoala on April 19, 2012, 10:39:21 PM

Thanks... I think I get it..... maybe..... So the bias power is "mixed in " with the main power from the batteries and must be dissipated in the load and mosfets (I suspect in the mosfets mostly). Hence the load heating and current viewing resistors are giving an inaccurate picture of the power flows in the circuit.... is that right?
(I know this has been covered before; I just want to hammer it home somehow if it is correct.)

I'm running so late that there's no point in making the drive. So here I am, stuck in Mobile with the Memphis blues again.

Anyway.... I tried the 50r/pot/cap/main battery thing and I can't get it to work. And yes, I've confirmed that the pot is good and is adjusting the voltage properly, tried with three different valued pots.

This _does_ work just fine with the external battery (no decoupling cap), but using the running battery I can't get it to work. External 9v gives beautiful nearly perfect sinusoidal oscillations on the common drain when the 10 k (not 1 meg; I also tried 100 K, no luck) pot is set right, and the "voltage floor" still shows up: the negative voltage on the gate drive signal floors at about 4 volts negative indicated on the scope trace.

I think you really do need to provide a potential that is more negative than the negative battery terminal....

I just made another video... chaotic but the points come through I hope. It's uploading now.

TK,

I would decouple the wiper of the pot, or just use a 10K resistor from the first Bat+ to a cap and tie the other end of the cap to real ground (not the CSR, althogh you might want to try both ground points). Then, to the junction of the resistor and cap, connect another resistor, 1Meg or so, and connect the other end of that high value resistor to the MOSFET gate. You may have to add a bit of wire length between the end of the 1Meg and the gate to add some inductance to get the osc. Possibly you will have to add some inductance (wire) in series with the 50R at the source as well.

PW

picowatt · « **Reply #432 on:** April 19, 2012, 10:59:54 PM »

Quote from: hartiberlin on April 19, 2012, 10:39:56 PM

Is the 200 mA really a DC current ?
What about the AC component flowing while the oscillations are happening ?

If we would use just a 9 Volts battery with a pot and put on the oscillations,
then we would pronbly only have an AC current, right ?
Or will we have an AC current superimposed on a DC 200 mA current ?

Maybe TK can measure this and show it on a new video ?

Many thanks.

Regards, Stefan.

Stefan,

If a 9 volt battery was placed in the source leg of Q2 with a series resistor, let's say 50R, then the DC bias current would be around 100ma plus or minus 30-40ma or so. When oscillating, there would be this DC bias current passing through the 50R and 9volt battery and a separate AC current. My assertion is that the AC current would follow two paths, one being the through 9 volt battery and 50R in this instance, and the other AC path being the gate to source capacitance of the MOSFETs.

PW

poynt99 · « **Reply #433 on:** April 19, 2012, 11:07:03 PM »

I don't think we want 200mA of AC current flowing through our bias battery, that's why I isolated it.

With isolation, the battery supplies only a tiny DC current to slightly bias the MOSFET ON, and the AC path is provided capacitively, which bypasses the DC bias network.

picowatt · « **Reply #434 on:** April 19, 2012, 11:24:40 PM »

Quote from: poynt99 on April 19, 2012, 11:07:03 PM

I don't think we want 200mA of AC current flowing through our bias battery, that's why I isolated it.

With isolation, the battery supplies only a tiny DC current to slightly bias the MOSFET ON, and the AC path is provided capacitively, which bypasses the DC bias network.

.99,

Yes, but in TK's set up using the 555, and in the NERD circuit using the FG, the 555 or FG must provide that 200ma of current at whatever negative voltage is used to keep Q2 biased on. Only by by applying the bias voltage to the gate can a "tiny DC current" be needed from the bias source.

Also, I am only estimating the Q2 Ibias. In the RA paper it was mentioned the FG was set to full negative offset in at least one test. I am assuming a maximum of -14.5 from the FG open circuit and an Rgen=50R. The voltage at the source of Q2 will always be Vgs from the gate, which is ground in this case. At -14.5V open circut at the FG, then there would be around 10V across the internal Rgen of 50R. 10V divided by the 50R is 200ma. This will vary a bit due to Vgs characteristics and device to device differences, so I believe I said some time ago I would "guess" Ibias to be around 150ma plus or minus 30ma or so. Likely the circuit could be "played with" to get it to osc at a lower bias current. Without knowing the open circuit voltage versus in circuit voltage of RA's FG, we cannot claculate Q2's Ibias.

PW

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