I can't do anything about posting over the schematic Ron.  But this is the post
« Reply #347 on: March 26, 2011, 04:09:20 AM »

I think the same schematic is applicable - just add in that MOSFET. 

I'll be able to get hold of the guys early next week and I'll ask them for that schematic they're trying out.  Then I'll post it here.

Hope that helps.  I'm afraid you'll need to be very creative as I absolutely can't help here.

Again, kindest and very best of regards,
Rosie

That sounds good to me Rosemary, thank you.

Harti's circuit is only a one polarity thing but is a starting point.
A logic FET switches at 5 volts but regular FETs like 10 or more to fully turn on, so we will see...

Warm regards,

Ron

Let's take a small step backward in the progression from the original 5-MOSFET circuit, to the single-MOSFET version I've provided, and re-insert the Q1 MOSFET in place of the parallel diode and capacitor. We can go back to that later.

The Simplification01_schema01.png illustrates this regression. Notice that I have redrawn the diagram slightly, but the connections are still the same as the original circuit.

As I've already well established the fact that only a DC voltage bias is required to set the circuit into oscillation, the function generator is omitted. Because the pulsed output and positive excursions are unnecessary for oscillation, the generator is not required. I trust this is seen by all as an important development.

Simplification01_scope01.png is a result of the simulation run and shows the "CSR" and "Vbat" voltage wave forms. Also indicated is the MEAN voltage of each, and note that the "CSR" voltage is about -56mV.

Following this is Simplification02_schema01.png. This diagram depicts one of the simplifications I've not yet shown. What you see is the DC bias source relocated to the "CSR" leg, and the DC bias source "flipped" over such that it's negative terminal is now connected to the circuit ground. Yet another important development in the progression.

The "CSR" and "Vbat" wave forms and MEAN values with this change are virtually identical to those in the Simplification01_scope01.png scope shot.

.99

Ok Poynty.  Here's the error.  You need to shift that signal battery supply to the rail in series with Q2. Then you can leave the CSR where it is.  Otherwise you need to move that CSR directly to the nagative rail of the source.

I can't get a printout so I'll probably edit here as well.

BRB
Rosie

Added.  ALSO.  You're showing the probe positioned at a NODE - YET AGAIN Poynty!  And you need to lose that CAP.  Why is it even there?  The one across the load?

Nothing wrong with the probe positions - sorry.  It's not a node.  'Me bad' as you guys say.  lol.

I love the clarity of those FET  positions.  So readable.  Thanks for that. 

Ok Poynty Point.  With those amendments I think we're good to go.  I'd prefer to see the waveform across the load - if you can oblige.  And I cannot see how that CAP can help anything at all. 

I think it would be beneficial for all at this time to refresh ourselves with the workings of a N-channel MOSFET.

Rose, would you please explain for the readers in a paragraph or two, and in basic terms, how a MOSFET functions? With respect to it's 3 pins, describe what external conditions are necessary on each pin in order to enable the MOSFET to pass a significant current.

Thanks,

.99

I missed this.  I absolutely cannot answer this with authority.  But as I understand it the drain is always open until it's linked to the source through the applied charge at the gate.  Those body diodes kick in when there's a reverse voltage and they're basically designed to 'snuff' all that counter electromotive force.  BUT.  The thing is this.  With that transposition and with the applied 'negative' voltage - then the FET Q2 is actually operating precisely in line with it's polarities with respect to the drain.  It just sees the drain as the source.  But I'll sketch it.  I've already done this.  I just need to get this presentable. 

Kindest regards,
Rosie

I missed this.  I absolutely cannot answer this with authority.  But as I understand it the drain is always open until it's linked to the source through the applied charge at the gate.

This is getting to the essence of it's operation, but one or two key points are still absent in that description.

With respect to the voltage between the Gate and the Source (V_GS), have a look at this Wiki page where they show how the Drain-to-Source channel is altered by the voltage applied to the Gate.

In the graph they are plotting I_D with respect to the applied V_G (V_G really means V_GS (Gate-to-Source voltage)).

What may we conclude from that animated graph? Is the MOSFET Drain-to-Source "channel" always connected, or is there a certain V_GS voltage that must be reached first?

http://en.wikipedia.org/wiki/File:Threshold_formation_nowatermark.gif

.99

@poynt99 .Re the graph on the Wicki page you provided a link to . What I find hard to understand is this . The vertical scale on the graph shows drain current . But the higher numbers are at the bottom of the scale and the lower numbers are at the top . From this , I would deduce that the higher the voltage on the gate , the Lower the Drain current .This can not be true in the case of the type of Mosfet we are talking about . What have I missed and what is the significance of the letter "E" in the Drain current numbers . I think what you may be trying to say is that some current can flow between drain and source with zero gate voltage ? The animation however appears to show that about0.5 volts  is  needed on the gate  to permit any drain-source current to flow .

This is getting to the essence of it's operation, but one or two key points are still absent in that description.

What may we conclude from that animated graph? Is the MOSFET Drain-to-Source "channel" always connected, or is there a certain V_GS voltage that must be reached first?

http://en.wikipedia.org/wiki/File:Threshold_formation_nowatermark.gif

These are not really relevant Poynt.  In the first instance it's a description of a nanowire MOSFET - and in the second instance they're arguing that the 'bridge' is gapped with electrons.  If you recall the entire premise of my argument is that there are NO ELECTRONS flowing in electric current flow.  What I require are magnetic dipoles.  And a magnetic dipole will bridge the gap across the gate in either direction - which is evidently what is happening.  I'll go into these arguments again Poynty - but it's as clear as daylight to me that you have NEVER even bothered to read up what the thinking is behind all these circuit designs.  How can you comment - if you don't even know the counter argument?  I've taken the trouble to learn classical argument.  Surely you can take the trouble to learn a variation of this?  I'll presume to give you a link to this when I've concluded this post.

Then.  I would be very glad to argue the condition of the circuit with you - and that at length.  But I absolutely refuse to do so on the premise of that schematic that you keep giving us.  It is ENTIRELY misleading.  The CSR is on the negative rail of the supply.  It is nowhere else.  There is absolutely NO requirement for that cap that you persist in putting across the load.  And the Q2 MOSFET does NOT have that zener biased as you've shown it.  Then.  The positioning of the source is TRANSPOSED on Q2 that it ACCEPTS the input from the 'negative signal' from the oscilloscope or the 'positive signal' from the battery - simply because - in terms of their polarities it is still positive according to the MOSFET.  In other words - according to the transposition - the MOSFET now sees the negative as a positive.  As in most things - charge is also relative.  I know you know this.

So.  What I'm really asking is WHY are you going through this circuitous circuit argument?  And WHY do you keep putting that schematic in front of us?  It's quite simply erroneous.  PLEASE amend it as required.  Then we've got a basis for discussion.

Kindest regards,
Rosemary

And just as a reminder - here it is again.  But what it STILL NEEDS is the reversal of the diode at Q2.  Otherwise it is precisely what is required.  And it is PRECISELY what we've got on our circuit except that the zener at Q2 - as mentioned twice already - needs to be changed.


And here's that link.  Please read it.
http://newlightondarkenergy.blogspot.com/2011/04/101-repost-of-8-inconvenient-truth.html

The operation of any enhancement-mode MOSFET is equal on all accounts, except for the recent development of low-threshold varieties, shown in that graph. The important point is that the principle is the same for all MOSFETs.

The I_D vs. V_GS characteristic curve shown is valid and representative of the IRFPG50 MOSFET being used in this circuit. The point of the graph is to show the general relationship between the Drain current I_D, and the applied Gate voltage V_GS. Parameters vary by type of MOSFET, but the characteristics are similar in all.

In summary, the Drain-to-Source channel is "open", OFF (high resistance) when V_GS = 0V. As V_GS increases in a positive direction (N-channel), the channel resistance begins to decrease, until finally the Gate-to-Source threshold voltage is reached (V_TH), and I_D begins to substantially increase. In effect, the MOSFET is beginning to turn ON once the Gate-to-Source voltage V_TH is reached.

.99