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Author Topic: Graham Gunderson's Energy conference presentation Most impressive and mysterious  (Read 55930 times)

Offline Spokane1

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Spokane1
Dear All,
Here is a drawing of the Synchronous Diode Component Layout to help facilitate discussions about this sub assembly.
Enjoy!

Free Energy | searching for free energy and discussing free energy


Offline lancaIV

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The risc of false/wrong measurements by "eye/instruments" about light sources as Output-Wattage
indicators :
http://google.com/patents/WO2015157722A1?cl=en

Part of the crux of this invention is that the detection timing of human visual process, as well as the measurement speed of light with LUX meters, react too slow to average the light intensities produced by various high frequencies pulsed current duty cycles. At these frequencies, regardless of the duty cycle percentage, the LUX meter, and more importantly human physiology, sees the light as a constant illumination rather than dimmed. Thus pulse width dimming at these frequencies, while it actually exists, is not perceived much and can only be measured by the fastest light metering devices.


https://www.google.com/patents/US5130608
 The network according to my present invention generates a train of pulse waves of extremely narrow pulse width. These pulses are amplified and directed into a fast switching power transistor. When the power transistor conducts the pulse train, current flows through the load for a time interval equal to the pulse width which may be measured in nanoseconds or microseconds. Since the useful energy is expended mainly during the pulse width but not during the resting period between pulses, which is relatively much larger than the pulse width, yet too short to be perceptible to the human eye, considerable energy can be saved while nevertheless maintaining brightness of illumination.
In other words, the light-producing ultra short DC pulses are selected sufficiently close in sequence (say 4,000 pulses per second) to prevent the human eye because of its natural retentivity, to discern the intervening resting or nonpulsed periods as shadows. As is well-known in the lighting art, fluorescent light is perceived continuous at 60 cycles AC per second, which is above the time-resolving ability of the eye or critical fusion frequency (CFF). Another- benefit on my present invention is to increase the longevity of incandescent load resistor elements.


In one example, the module circuit is adjusted to produce 4,000 pulses per second with a pulse width of about 10  microseconds (with an average resting interval of about 240 microseconds), a load of 100 ohms, and a charging potential of 100 volts. Using Ohm's Law, these conditions would produce 100 watts of peak power. Using Equation I, the average power in the Example 1 can thus be calculated, i.e., about 4 watts. Assuming that the power dissipated in the module itself is approximately 8 watts, the total average energy consumed is the sum of energy expenditure due to load and energy dissipated in the working module, namely a grand total of about 12 watts.

Clearly, the average power consumed in the pulsed incandescence of a light bulb under the control of the inventive module of this example is as low as almost one-tenth the amount consumed in a conventional AC power supply for an incandescent light bulb.

https://en.wikipedia.org/wiki/Flicker_fusion_threshold

about  MEG  patent-grant ability :
from Paul Galey
 https://worldwide.espacenet.com/publicationDetails/biblio?DB=EPODOC&II=4&ND=3&adjacent=true&locale=fr_EP&FT=D&date=19761217&CC=FR&NR=2312135A1&KC=A1
to "Citing documents"

Luis Ramon Suarez
https://worldwide.espacenet.com/publicationDetails/biblio?DB=EPODOC&II=2&ND=4&adjacent=true&locale=fr_EP&FT=D&date=20070201&CC=ES&NR=2265253A1&KC=A1

https://worldwide.espacenet.com/publicationDetails/inpadoc?CC=ES&NR=2265253A1&KC=A1&FT=D&ND=3&date=20070201&DB=&locale=fr_ch                       DEFINITIVE PROTECTION


About MEG and system free available energy :

https://worldwide.espacenet.com/publicationDetails/biblio?CC=BE&NR=1018711A3&KC=A3&FT=D&ND=5&date=20110705&DB=EPODOC&locale=fr_EP
Pour de petites puissances de 25 à 40 kilowatts/jour, les gains moyens oscilleront de 18 à 20 %. Par contre, pour des puissances supérieures à 100 kW/jours, les gains moyens pourront, en principe, vite atteindre plus de 25 %.

These values are similar this one :
https://worldwide.espacenet.com/publicationDetails/biblio?DB=EPODOC&II=17&ND=3&adjacent=true&locale=fr_EP&FT=D&date=19860717&CC=DE&NR=3501076A1&KC=A1
Wenn in Anlehnung  an bisherige Wechselhysteresetheorien (siehe anfangs) in eine 500 g schwere Ferritmagnetplatte bei einer Zyklenfrequenz von 5000 Hz etwa 25 kW "hinein-  fliessen", so ergibt sich bei einem angenommenen Wandlerwirkungsgrad von 20% als sekundär entnommen eine Leistung von 5 kW.   

500g Ferritmagnet for 5 KW power output(Frequency dependance,here 5 KHz) comparing with the offered details about  Paul Galeys static generator :
Pour chaque dispositif d'une puissance de 2 kW en courant alternatif 220 volts,50 hertz par exemple,utilisant des aimants ferrites courants,il faudrait environ 75 grammes d'aimant.
« Last Edit: August 09, 2016, 10:54:47 PM by lancaIV »


Offline k4zep

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Spokane1
Dear All,
Here is a drawing of the Synchronous Diode Component Layout to help facilitate discussions about this sub assembly.
Enjoy!

Beautiful work S1!  Maybe this can get us back on track!

Ben K4ZEP

Offline verpies

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The real question is to understand what is going on in the Synchronous Diode section.  Do you happen to know what the upper limit of leakage power might be from a FET gate to the source-drain current path?
There is no upper limit since the current flowing due to the MOSFET's Gate Leakage is proportional to the voltages & frequencies appearing between the gate and drain terminals.  Fore example, the reactance of a 500pF capacitance @ 1MHz is 318Ω.

If you have the drain swinging by 600V with respect to the gate, then the instantaneous power transfer across that 318Ω reactance will be 1131W.
If that 600V swing happens only 0.5% of the total cycle time, then the average power transferred by that capacitive reactance will be 5.6W.


P.S.
The Miller's capacitance decreases as the gate drain voltage increases.


Offline k4zep

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There is no upper limit since the current flowing due to the MOSFET's Gate Leakage is proportional to the voltages & frequencies appearing between the gate and drain terminals.  Fore example, the reactance of a 500pF capacitance @ 1MHz is 318Ω.

If you have the drain swinging by 600V with respect to the gate, then the instantaneous power transfer across that 318Ω reactance will be 1131W.
If that 600V swing happens only 0.5% of the total cycle time, then the average power transferred by that capacitive reactance will be 5.6W.


P.S.
The Miller's capacitance decreases as the gate drain voltage increases.

But with the transformer action dropping the voltage to about 12-20 VAC, what is the value then?????  The transformer is not 1/1!  Transfer is in the mw range.

Ben K4ZEP

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Offline verpies

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But with the transformer action dropping the voltage to about 12-20 VAC, what is the value then? ??? ?  The transformer is not 1/1!  Transfer is in the mw range.
I was more concerned about the Gate Leakage from the MOSFETs that are AFTER the transformer.

AFAIK these MOSFETs form the synchronous rectifier and the secondary/output 1μs interrupter circuit.

Offline TinselKoala

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I couldn't find anything under the part number on Spokane1's diagram, C2M002510D. Neither the Cree website nor DigiKey lists anything with that part number that I could find. However, the nearest thing I could find is the C2M0025120D mosfet, 1200V 90A 34mOhm Rdson. Only 69 dollars and 80 cents _each_, from DigiKey. Data sheet attached:

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Offline verpies

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2.7nF gate capacitance ...OUCH!

...but only 15pf reverse transfer capacitance (w/o transconductance multiplier).

Offline Spokane1

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I was more concerned about the Gate Leakage from the MOSFETs that are AFTER the transformer.

AFAIK these MOSFETs form the synchronous rectifier and the secondary/output 1μs interrupter circuit.

Dear verpies,

What kind of leakage takes place if the MOSFETS are constantly on? In order to pass energy through a parasitic Miller capacitance don't we have to have AC present? In this circuit the MOSFETS are on for 20 uS  (50 k cps) and then are briefly shut off for 5 to 1000 nS (I don't know the exact timing).  Wouldn't this very narrow duty factor have a tendency to reduce the kinds of losses you are addressing?

Spokane1

Offline Spokane1

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I couldn't find anything under the part number on Spokane1's diagram, C2M002510D. Neither the Cree website nor DigiKey lists anything with that part number that I could find. However, the nearest thing I could find is the C2M0025120D mosfet, 1200V 90A 34mOhm Rdson. Only 69 dollars and 80 cents _each_, from DigiKey. Data sheet attached:

Dear TK,

Thanks for pointing  this out. I shall make corrections on the next revision.

Let me know if you can see anything else that needs improvement.

Spokane1

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Offline verpies

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What kind of leakage takes place if the MOSFETS are constantly on?
In order to pass energy through a parasitic Miller capacitance don't we have to have AC present?
No, any change in the voltage appearing between the gate and drain is enough.  Even one pulse.  Many cycles of AC are not required.

Also, if the source's potential is free to vary (as in a source follower) then the energy can flow from the gate to the source circuit, too.

In this circuit the MOSFETS are on for 20 uS  (50 k cps) and then are briefly shut off for 5 to 1000 nS (I don't know the exact timing).  Wouldn't this very narrow duty factor have a tendency to reduce the kinds of losses you are addressing?
Yes, the duration of the period when dv/dt is greater than zero, will affect the gate leakage proportionally.  In my calculation above, I accounted for a 0.5% duty factor and a pulse having dv/dt = 600V/1us.

The amount of the MOSFET's gate leakage depends on the overall circuit configuration and should be measured empirically for best accuracy.

Offline Spokane1

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Dear All,

Here is my first shot at the Schematic for the Synchronous Diode Sub Assembly. Comments and suggestions are welcomed.

Spokane1


Offline k4zep

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Dear All,

Here is my first shot at the Schematic for the Synchronous Diode Sub Assembly. Comments and suggestions are welcomed.

Spokane1

What a prodigious amount of work there Spok1.  Is there possibly a small problem with the rectifier diode for the negative -5 volt regulators?
Possibly a CT on the transformer in that portion of circuit connected to common.

Ben K4ZEP

Offline Spokane1

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Dear K4zep

You are absolutely right, I need to make some adjustments there.

Also Graham likes to use two large tantalum capacitors with each MOSFET driver, which are not shown in this drawing version.

I'm not to sure about the wired logic that controls the start-up and shut down of the power supply switching transformer, I believe that the intent is to have any of the regulator/storage circuits start the power switching when a low voltage condition is detected. I would also think that an over voltage condition would shut down the power supply MOSFET as well, thus two Zener's per isolation monitor.

I'm not really sure where the main power switching element is. That little transistor looking thing next to the Driver chip looks to small to run six low power regulators. It could be on the back of the circuit board along with all the needed storage capacitor's.

I'm not a switch-mode power supply designer. Graham's intent was to make a very low energy power supply to provide a great deal of isolation at the highest efficiency that would run the Synchronous Diode circuit. He has spent years designing and building these kinds of circuits, so I believe that what we are looking at is the best there is using DigiKey components.

Spokane1


Offline TinselKoala

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Thanks Spokane1 for the diagram, I can appreciate how much work that is. That's all well and good, but I'm having trouble believing that the circuit you've drawn out could provide enough current for the driver chips to switch into the Gate capacitances of the mosfets at 50 kHz. Where does the input power come from for this circuit? Is it coming from the breadboard?

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